Opis: Testing for Small-delay Defects in Nanoscale CMOS Integrated Circuits

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.Fundamentals of Small-Delay Defect Testing Sudhakar M. Reddy and Peter Maxwell Timing-Aware ATPG K Longest Paths Duncan M. (Hank) Walker Timing-Aware ATPG Mark Kassab, Benoit Nadeau-Dostie, and Xijiang Lin Faster-than At-Speed Faster-than-at-Speed Test for Screening Small-Delay Defects Nisar Ahmed and Mohammad Tehranipoor Circuit Path Grading Considering Layout, Process Variations, and Cross Talk Ke Peng, Mahmut Yilmaz, and Mohammad Tehranipoor Alternative Methods Output Deviations-Based SDD Testing Mahmut Yilmaz Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects Sandeep K. Goel and Narendra Devta-Prasanna Circuit Topology-Based Test Pattern Generation for Small-Delay Defects Sandeep K. Goel and Krishnendu Chakrabarty SDD Metrics Small-Delay Defect Coverage Metrics Narendra Devta-Prasanna and Sandeep K. Goel

Szczegóły: Testing for Small-delay Defects in Nanoscale CMOS Integrated Circuits

Tytuł: Testing for Small-delay Defects in Nanoscale CMOS Integrated Circuits
Producent: CRC Press Inc.
ISBN: 9781439829417
Rok produkcji: 2013
Ilość stron: 259
Oprawa: Twarda
Waga: 0.6 kg

Recenzje: Testing for Small-delay Defects in Nanoscale CMOS Integrated Circuits